Bluespec与CPU(MIT6.375)

 1import RightShifterTypes::*;
 2import Gates::*;
 3
 4// sel b + ^sel a
 5function Bit#(1) multiplexer1(Bit#(1) sel, Bit#(1) a, Bit#(1) b);
 6	return orGate(
 7				andGate(sel, b),
 8				andGate(notGate(sel), a)
 9	);
10endfunction
11
12function Bit#(32) multiplexer32(Bit#(1) sel, Bit#(32) a, Bit#(32) b);
13	Bit#(32) res = 0;
14	for(Integer i = 0; i < 32; i = i + 1) begin
15		res[i] = multiplexer1(sel, a[i], b[i]);
16	end
17	return res;
18endfunction
19
20function Bit#(n) multiplexerN(Bit#(1) sel, Bit#(n) a, Bit#(n) b);
21	Bit#(n) res = 0;
22	for(Integer i = 0; i < valueof(n); i = i + 1) begin
23		res[i] = multiplexer1(sel, a[i], b[i]);
24	end
25	return res;
26endfunction
27
28
29
30module mkRightShifter (RightShifter);
31	method Bit#(32) shift(ShiftMode mode, Bit#(32) operand, Bit#(5) shamt);
32		Bit#(32) res = operand, tmp = 0;
33		Integer base[5] = {1, 2, 4, 8, 16};
34		Bit#(1) signal = 0;
35
36		if(mode == ArithmeticRightShift) begin
37			signal = operand[31];
38		end
39
40		for(Integer i = 0; i < 5; i = i + 1) begin
41			// tmp 记录了当前移位后的结果
42			tmp = res[31: base[i]];
43			for(Integer j = 1; j <= base[i]; j = j + 1) begin
44				tmp[32 - j] = signal;
45			end
46			res = multiplexerN(shamt[i], res, tmp);
47		end
48		return res;   
49	endmethod
50endmodule

 1import RightShifterTypes::*;
 2import Gates::*;
 3import FIFO::*;
 4
 5function Bit#(1) multiplexer1(Bit#(1) sel, Bit#(1) a, Bit#(1) b);
 6	return orGate(andGate(a, sel),andGate(b, notGate(sel))); 
 7endfunction
 8
 9function Bit#(32) multiplexer32(Bit#(1) sel, Bit#(32) a, Bit#(32) b);
10	Bit#(32) res_vec = 0;
11	for (Integer i = 0; i < 32; i = i+1)
12		begin
13		res_vec[i] = multiplexer1(sel, a[i], b[i]);
14		end
15	return res_vec; 
16endfunction
17
18function Bit#(n) multiplexerN(Bit#(1) sel, Bit#(n) a, Bit#(n) b);
19	Bit#(n) res_vec = 0;
20	for (Integer i = 0; i < valueof(n); i = i+1)
21		begin
22		res_vec[i] = multiplexer1(sel, a[i], b[i]);
23		end
24	return res_vec; 
25endfunction
26
27module mkRightShifterPipelined (RightShifterPipelined);
28	FIFO#(Tuple3#(ShiftMode, Bit#(32), Bit#(5))) c[6];
29
30	// 将operand右移cnt位, 模式为mode
31	function Bit#(32) shiftOnce(ShiftMode mode, Bit#(32) operand, Integer cnt);
32		bit signal = 0;
33		if(mode == ArithmeticRightShift) begin
34			signal = operand[31];
35		end
36
37		operand = operand[31: cnt];
38		for(Integer i = 1; i <= cnt; i = i + 1) begin
39			operand[32 - i] = signal;
40		end
41
42		return operand;
43	endfunction
44
45
46	for(int i = 0; i < 6; i = i + 1) begin
47		c[i] <- mkFIFO();
48	end
49
50	for(Integer i = 0; i < 5; i = i + 1) begin
51		rule pipeShift;
52			match {.mode, .operand, .shamt} = c[i].first();
53			c[i].deq();
54
55			Integer base[5] = {1, 2, 4, 8, 16};
56			if(shamt[i] == 1) begin
57				operand = shiftOnce(mode, operand, base[i]);
58			end
59
60			c[i + 1].enq(tuple3(mode, operand, shamt));
61		endrule
62	end
63
64	method Action push(ShiftMode mode, Bit#(32) operand, Bit#(5) shamt);
65		c[0].enq(tuple3(mode, operand, shamt));
66	endmethod
67	
68	method ActionValue#(Bit#(32)) pull();
69		match {.mode, .res, .shamt} = c[5].first();
70		c[5].deq();
71		return res;
72	endmethod
73
74endmodule

 1import RightShifterTypes::*;
 2import RightShifter::*;
 3import FIFO::*;
 4
 5(* synthesize *)
 6module mkTests (Empty);
 7   RightShifterPipelined rsp <- mkRightShifterPipelined;
 8   Reg#(Bit#(32)) tbCounter <- mkReg(0);
 9   FIFO#(Bit#(32)) answerFifo <- mkSizedFIFO(6);
10   
11   // there are many ways to write tests.  Here is a very simple
12   // version, just to get you started.
13
14   rule run;
15	rsp.push(LogicalRightShift, tbCounter, 1);
16	answerFifo.enq(tbCounter >> 1);
17	tbCounter <= tbCounter + 1;
18   endrule
19
20   rule test;
21
22      let b <- rsp.pull();
23      let answer = answerFifo.first();
24      answerFifo.deq();
25
26      if (b != answer) $display("result is ", b, " but expected ", answer);
27      else $display("correct! ", b, " ", answer);
28
29      if (tbCounter > 10) $finish(0);
30
31   endrule
32endmodule
33
34# make && ./a.out
35# bsc -sim -u TestShifterPipe.bsv
36# checking package dependencies
37# All packages are up to date.
38# bsc -sim -e mkTests
39# Bluesim object reused: mkTests.{h,o}
40# Bluesim object created: model_mkTests.{h,o}
41# Simulation shared library created: a.out.so
42# Simulation executable created: a.out
43# correct! 2863311530          0
44# correct! 2863311530          0
45# correct! 2863311530          1
46# correct! 2863311530          1
47# correct! 2863311530          2
48# correct! 2863311530          2
49# correct! 2863311530          3
50# correct! 2863311530          3
51# correct! 2863311530          4
52# correct! 2863311530          4
53# correct! 2863311530          5

 1import Types::*;
 2import ProcTypes::*;
 3import MemTypes::*;
 4import RFile::*;
 5import IMemory::*;
 6import DMemory::*;
 7import Decode::*;
 8import Exec::*;
 9import Cop::*;
10
11typedef enum {Fetch, Execute} State deriving (Bits, Eq);
12
13interface Proc;
14   method ActionValue#(Tuple2#(RIndx, Data)) cpuToHost;
15   method Action hostToCpu(Bit#(32) startpc);
16endinterface
17
18(* synthesize *)
19module [Module] mkProc(Proc);
20  Reg#(Addr) pc <- mkRegU;
21  RFile      rf <- mkRFile;
22  IMemory  iMem <- mkIMemory;
23  DMemory  dMem <- mkDMemory;
24  Cop       cop <- mkCop;
25  
26  Reg#(State) state <- mkReg(Fetch);
27  Reg#(Data)     ir <- mkRegU;
28
29  rule doFetch(cop.started && state == Fetch);
30    let inst = iMem.req(pc);
31
32    $display("pc: %h inst: (%h) expanded: ", pc, inst, showInst(inst));
33
34    // store the instruction in a register
35    ir <= inst;
36
37    // switch to execute state
38    state <= Execute;
39  endrule
40
41  rule doExecute(cop.started && state == Execute);
42    let inst = ir;
43
44    let dInst = decode(inst);
45
46    let rVal1 = rf.rd1(validRegValue(dInst.src1));
47    let rVal2 = rf.rd2(validRegValue(dInst.src2));     
48
49    let copVal = cop.rd(validRegValue(dInst.src1));
50
51    let eInst = exec(dInst, rVal1, rVal2, pc, ?, copVal);
52
53    if(eInst.iType == Unsupported)
54    begin
55      $fwrite(stderr, "Executing unsupported instruction at pc: %x. Exiting\n", pc);
56      $finish;
57    end
58
59    if(eInst.iType == Ld)
60    begin
61      let data <- dMem.req(MemReq{op: Ld, addr: eInst.addr, byteEn: ?, data: ?});
62      eInst.data = gatherLoad(eInst.addr, eInst.byteEn, eInst.unsignedLd, data);
63    end
64    else if(eInst.iType == St)
65    begin
66      match {.byteEn, .data} = scatterStore(eInst.addr, eInst.byteEn, eInst.data);
67      let d <- dMem.req(MemReq{op: St, addr: eInst.addr, byteEn: byteEn, data: data});
68    end
69
70    if (isValid(eInst.dst) && validValue(eInst.dst).regType == Normal)
71      rf.wr(validRegValue(eInst.dst), eInst.data);
72
73    pc <= eInst.brTaken ? eInst.addr : pc + 4;
74
75    cop.wr(eInst.dst, eInst.data);
76
77    // switch back to fetch
78    state <= Fetch;
79  endrule
80  
81  method ActionValue#(Tuple2#(RIndx, Data)) cpuToHost;
82    let ret <- cop.cpuToHost;
83    return ret;
84  endmethod
85
86  method Action hostToCpu(Bit#(32) startpc) if (!cop.started);
87    cop.start;
88    // pc <= startpc;
89  endmethod
90endmodule

 1// ProcTypes.bsv
 2function RIndx validRegValue(Maybe#(FullIndx) idx) = validValue(idx).idx;
 3
 4// RFile.bsv
 5 (* synthesize *)
 6module mkRFile( RFile );
 7    Vector#(32, Reg#(Data)) rfile <- replicateM(mkConfigReg(0));
 8
 9    function Data read(RIndx rindx);
10        return rfile[rindx];
11    endfunction
12   
13    method Action wr( RIndx rindx, Data data );
14        if(rindx!=0) rfile[rindx] <= data;
15    endmethod
16
17    method Data rd1( RIndx rindx ) = read(rindx);
18    method Data rd2( RIndx rindx ) = read(rindx);
19endmodule

 1(* noinline *)
 2function ExecInst exec(DecodedInst dInst, Data rVal1, Data rVal2, Addr pc, Addr ppc, Data copVal);
 3  ExecInst eInst = ?;
 4  Data aluVal2 = isValid(dInst.imm) ? validValue(dInst.imm) : rVal2;
 5  
 6  let aluRes = alu(rVal1, aluVal2, dInst.aluFunc);
 7  
 8  eInst.iType = dInst.iType;
 9  
10  eInst.data = dInst.iType == Mfc0?
11                 copVal :
12               dInst.iType == Mtc0?
13                 rVal1 :
14               dInst.iType==St?
15                 rVal2 :
16               (dInst.iType==J || dInst.iType==Jr) ?
17                 (pc+4) :
18                 aluRes;
19  eInst.byteEn = dInst.byteEn;
20  eInst.unsignedLd = dInst.unsignedLd;
21  
22  let brTaken = aluBr(rVal1, rVal2, dInst.brFunc);
23  let brAddr = brAddrCalc(pc, rVal1, dInst.iType, validValue(dInst.imm), brTaken);
24  eInst.mispredict = brAddr != ppc;
25
26  eInst.brTaken = brTaken;
27  eInst.addr = (dInst.iType == Ld || dInst.iType == St) ? aluRes : brAddr;
28  
29  eInst.dst = dInst.dst;
30
31  return eInst;
32endfunction

 1typedef enum {Fetch, Execute, Writeback} State deriving (Bits, Eq);
 2...
 3Reg#(ExecInst) wbr <- mkRegU;
 4...
 5
 6...
 7	if(eInst.iType == Ld)
 8	begin
 9		let data <- dMem.req(MemReq{op: Ld, addr: eInst.addr, byteEn: ?, data: ?});
10		eInst.data = gatherLoad(eInst.addr, eInst.byteEn, eInst.unsignedLd, data);
11	end
12	else if(eInst.iType == St)
13	begin
14		match {.byteEn, .data} = scatterStore(eInst.addr, eInst.byteEn, eInst.data);
15		let d <- dMem.req(MemReq{op: St, addr: eInst.addr, byteEn: byteEn, data: data});
16	end
17
18	if (isValid(eInst.dst) && validValue(eInst.dst).regType == Normal) begin
19		wbr <= eInst;
20		state <= Writeback;
21	end
22	else begin
23		pc <= eInst.brTaken ? eInst.addr : pc + 4;
24		cop.wr(eInst.dst, eInst.data);
25		state <= Fetch;
26	end
27endrule
28
29rule doWriteBack(cop.started && state == Writeback);
30	let eInst = wbr;
31	rf.wr(validRegValue(eInst.dst), eInst.data);
32
33	pc <= eInst.brTaken ? eInst.addr : pc + 4;
34	cop.wr(eInst.dst, eInst.data);
35	state <= Fetch;
36endrule
37...

  1(* synthesize *)
  2module [Module] mkProc(Proc);
  3  Reg#(Addr) pc <- mkRegU;
  4  RFile      rf <- mkRFile;
  5  IMemory  iMem <- mkIMemory;
  6  DMemory  dMem <- mkDMemory;
  7  Cop       cop <- mkCop;
  8  AddrPred pcPred <- mkBtb;
  9
 10  //Fifo#(1, Fetch2Execute) ir <- mkPipelineFifo;
 11  Fifo#(2, Fetch2Execute) ir <- mkCFFifo;
 12  Fifo#(1, Redirect) execRedirect <- mkBypassFifo;
 13  //Fifo#(2, Redirect)   execRedirect <- mkCFFifo;
 14
 15  //This design uses two epoch registers, one for each stage of the pipeline. Execute sets the eEpoch and discards any instruction that doesn't match it. It passes the information about change of epoch to fetch stage indirectly by passing a valid execRedirect using a Fifo. Fetch changes fEpoch everytime it gets a execRedirect and tags every instruction with its epoch
 16
 17  Reg#(Bool) fEpoch <- mkReg(False);
 18  Reg#(Bool) eEpoch <- mkReg(False);
 19
 20  rule doFetch(cop.started);
 21    let inst = iMem.req(pc);
 22
 23    $display("Fetch: pc: %h inst: (%h) expanded: ", pc, inst, showInst(inst));
 24
 25    // dequeue the incoming redirect and update the predictor whether it's a mispredict or not
 26    if(execRedirect.notEmpty)
 27    begin
 28      execRedirect.deq;
 29      pcPred.update(execRedirect.first);
 30    end
 31    // change pc and the fetch's copy of the epoch only on a mispredict
 32    if(execRedirect.notEmpty && execRedirect.first.mispredict)
 33    begin
 34      fEpoch <= !fEpoch;
 35      pc <= execRedirect.first.nextPc;
 36    end
 37    // fetch the new instruction on a non mispredict
 38    else
 39    begin
 40      let ppc = pcPred.predPc(pc);
 41      pc <= ppc;
 42      ir.enq(Fetch2Execute{pc: pc, ppc: ppc, inst: inst, epoch: fEpoch});
 43    end
 44  endrule
 45
 46  rule doExecute;
 47    let inst  = ir.first.inst;
 48    let pc    = ir.first.pc;
 49    let ppc   = ir.first.ppc;
 50    let epoch = ir.first.epoch;
 51
 52    // Proceed only if the epochs match
 53    if(epoch == eEpoch)
 54    begin
 55      $display("Execute: pc: %h inst: (%h) expanded: ", pc, inst, showInst(inst));
 56  
 57      let dInst = decode(inst);
 58  
 59      let rVal1 = rf.rd1(validRegValue(dInst.src1));
 60      let rVal2 = rf.rd2(validRegValue(dInst.src2));     
 61  
 62      let copVal = cop.rd(validRegValue(dInst.src1));
 63  
 64      let eInst = exec(dInst, rVal1, rVal2, pc, ppc, copVal);
 65  
 66      if(eInst.iType == Unsupported)
 67      begin
 68        $fwrite(stderr, "Executing unsupported instruction at pc: %x. Exiting\n", pc);
 69        $finish;
 70      end
 71
 72      if(eInst.iType == Ld)
 73      begin
 74        let data <- dMem.req(MemReq{op: Ld, addr: eInst.addr, byteEn: ?, data: ?});
 75        eInst.data = gatherLoad(eInst.addr, eInst.byteEn, eInst.unsignedLd, data);
 76      end
 77      else if(eInst.iType == St)
 78      begin
 79        match {.byteEn, .data} = scatterStore(eInst.addr, eInst.byteEn, eInst.data);
 80        let d <- dMem.req(MemReq{op: St, addr: eInst.addr, byteEn: byteEn, data: data});
 81      end
 82
 83      if (isValid(eInst.dst) && validValue(eInst.dst).regType == Normal)
 84        rf.wr(validRegValue(eInst.dst), eInst.data);
 85  
 86      // Send the branch resolution to fetch stage, irrespective of whether it's mispredicted or not
 87       // TBD: put code here that does what the comment immediately above says
 88
 89      // On a branch mispredict, change the epoch, to throw away wrong path instructions
 90       // TBD: put code here that does what the comment immediately above says
 91  
 92      cop.wr(eInst.dst, eInst.data);
 93    end
 94
 95    ir.deq;
 96  endrule
 97  
 98  method ActionValue#(Tuple2#(RIndx, Data)) cpuToHost;
 99    let ret <- cop.cpuToHost;
100    return ret;
101  endmethod
102
103  method Action hostToCpu(Bit#(32) startpc) if (!cop.started);
104    cop.start;
105    pc <= startpc;
106  endmethod
107endmodule

 1import Fifo::*;
 2import ProcTypes::*;
 3
 4interface Scoreboard#(numeric type size);
 5  method Action insert(Maybe#(FullIndx) r);
 6  method Action remove;
 7  method Bool search1(Maybe#(FullIndx) r);
 8  method Bool search2(Maybe#(FullIndx) r);
 9  method Bool search3(Maybe#(FullIndx) r);
10  method Action clear;
11endinterface
12
13function Bool isFound(Maybe#(FullIndx) x, Maybe#(FullIndx) k);
14   if(x matches tagged Valid .xv &&& k matches tagged Valid .kv &&& kv == xv)
15     return True;
16   else
17     return False;
18endfunction
19
20// search CF {enq, deq, first, notEmpty, notFull}
21// deq CF enq
22// search < clear
23module mkCFScoreboard(Scoreboard#(size));
24  SFifo#(size, Maybe#(FullIndx), Maybe#(FullIndx))  f <- mkCFSFifo(isFound);
25
26  method insert = f.enq;
27
28  method remove = f.deq;
29
30  method search1 = f.search;
31  method search2 = f.search;
32  method search3 = f.search;
33
34  method clear = f.clear;
35endmodule
36
37// notEmpty < first < deq < search < notFull < enq < clear
38module mkPipelineScoreboard(Scoreboard#(size));
39  SFifo#(size, Maybe#(FullIndx), Maybe#(FullIndx)) f <- mkPipelineSFifo(isFound);
40
41  method insert = f.enq;
42
43  method remove = f.deq;
44
45  method search1 = f.search;
46  method search2 = f.search;
47  method search3 = f.search;
48
49  method clear = f.clear;
50endmodule
51
52interface CountScoreboard#(numeric type size);
53  method Action insert(Maybe#(FullIndx) r);
54  method Action remove;
55  method Bit#(TLog#(TAdd#(size, 1))) search1(Maybe#(FullIndx) r);
56  method Bit#(TLog#(TAdd#(size, 1))) search2(Maybe#(FullIndx) r);
57  method Bit#(TLog#(TAdd#(size, 1))) search3(Maybe#(FullIndx) r);
58  method Action clear;
59endinterface
60
61// search CF {enq, deq, first, notEmpty, notFull}
62// deq CF enq
63// search < clear
64module mkCFCountScoreboard(CountScoreboard#(size));
65  SCountFifo#(size, Maybe#(FullIndx), Maybe#(FullIndx))  f <- mkCFSCountFifo(isFound);
66
67  method insert = f.enq;
68
69  method remove = f.deq;
70
71  method search1 = f.search;
72  method search2 = f.search;
73  method search3 = f.search;
74
75  method clear = f.clear;
76endmodule